//
// HardMPU ISA GA v1.0
//
// LAPC-I Clone
//
// (C)2021 St(u)dio of Computer Games
// by Alexander Ozumenko
//

module lapci_isa_ga (
	// ISA interface
	isa_db, isa_ba0, isa_nhcs, isa_irq, isa_nhrd, isa_nhwr, isa_nreset,
	// MCU interface
	mpu_data, mpu_dsr, mpu_drr, mpu_crr, mpu_nidw, mpu_nidr, mpu_nreset
);

inout[7:0]	isa_db;
input			isa_ba0;
input			isa_nhcs;
output		isa_irq;
input 		isa_nhrd;
input			isa_nhwr;
input			isa_nreset;

inout[7:0]	mpu_data;
output		mpu_dsr;
output		mpu_drr;
output		mpu_crr;
input			mpu_nidw;
input			mpu_nidr;
output		mpu_nreset;



reg[7:0]		data_rd_reg;
reg[7:0]		data_wr_reg;
reg			dsr;								// DATA Set Register
reg			drr;								// DATA Read Register
reg			crr;								// CONTROL Read Register

wire			ndr;
wire			ndw;
wire			ncr;
wire			ncw;
wire			ndrclk;

assign		mpu_nreset = isa_nreset;
assign		isa_irq = dsr;

assign		ndr = !(!isa_nhcs && (isa_ba0 == 0) && !isa_nhrd && isa_nhwr);
assign		ndw = !(!isa_nhcs && (isa_ba0 == 0) && isa_nhrd && !isa_nhwr);
assign		ncr = !(!isa_nhcs && (isa_ba0 == 1) && !isa_nhrd && isa_nhwr);
assign		ncw = !(!isa_nhcs && (isa_ba0 == 1) && isa_nhrd && !isa_nhwr);

assign		ndrclk = !(!ncw | !ndw);	// read DATA or STATUS register



// DATA/COMMAND register
assign 		isa_db = !ndr ? data_rd_reg : 8'bzzzzzzzz;
always @(negedge mpu_nidw)
begin
	data_rd_reg <= mpu_data;
end

assign 		mpu_data = !mpu_nidr ? data_wr_reg : 8'bzzzzzzzz;
always @(negedge ndrclk)
begin
	data_wr_reg <= isa_db;
end


// STATUS register
wire[7:0]	status = {~dsr, drr, 6'b111111};
assign		isa_db = !ncr ? status : 8'bzzzzzzzz;


// DSR - MPU write data to BUS, BUS ACK
assign		mpu_dsr = dsr;
always @(negedge mpu_nidw or negedge ndr or negedge isa_nreset)
begin
	if (!isa_nreset)
	begin
		dsr <= 0;
	end
	else if (!ndr)
	begin
		dsr <= 0;
	end
	else if (!mpu_nidw)
	begin
		dsr <= 1;
	end
end


// DRR - BUS write DATA to MPU, MPU ACK
assign		mpu_drr = drr;
always @(negedge ndw or negedge mpu_nidr or negedge isa_nreset)
begin
	if (!isa_nreset)
	begin
		drr <= 0;
	end
	else if  (!mpu_nidr)
	begin
		drr <= 0;
	end
	else if (!ndw)
	begin
		drr <= 1;
	end
end


// CRR
assign		mpu_crr = crr;
always @(negedge ncw or negedge mpu_nidr or negedge isa_nreset)
begin
	if (!isa_nreset)
	begin
		crr <= 0;
	end
	else if(!mpu_nidr)
	begin
		crr <= 0;
	end
	else if (!ncw)
	begin
		crr <= 1;
	end
end



endmodule