// NCR5380 registers
`define OUTPUT_DATA_REG								3'd0
`define CURRENT_SCSI_DATA_REG						3'd0

`define INITIATOR_COMMAND_REG						3'd1
`define ICR_ASSERT_RST								7
`define ICR_ARBITRATION_PROGRESS					6
`define ICR_TRI_STATE								6
`define ICR_ARBITRATION_LOST						5
`define ICR_DIFF_ENABLE								5
`define ICR_ASSERT_ACK								4
`define ICR_ASSERT_BSY								3
`define ICR_ASSERT_SEL								2
`define ICR_ASSERT_ATN								1
`define ICR_ASSERT_DATA								0

`define MODE_REG										3'd2
`define MR_BLOCK_DMA_MODE							7
`define MR_TARGET										6
`define MR_ENABLE_PAR_CHECK						5
`define MR_ENABLE_PAR_INTR							4
`define MR_ENABLE_EOP_INTR							3
`define MR_MONITOR_BSY								2
`define MR_DMA_MODE									1
`define MR_ARBITRATE									0

`define TARGET_COMMAND_REG							3'd3
`define TCR_ASSERT_REQ								3
`define TCR_ASSERT_MSG								2
`define TCR_ASSERT_CD								1
`define TCR_ASSERT_IO								0

`define STATUS_REG									3'd4
`define SR_RST											7
`define SR_BSY											6
`define SR_REQ											5
`define SR_MSG											4
`define SR_CD											3
`define SR_IO											2
`define SR_SEL											1
`define SR_DBP											0

`define SELECT_ENABLE_REG							3'd4

`define BUS_AND_STATUS_REG							3'd5
`define BASR_END_DMA_TRANSFER						7
`define BASR_DRQ										6
`define BASR_PARITY_ERROR							5
`define BASR_IRQ										4
`define BASR_PHASE_MATCH							3
`define BASR_BUSY_ERROR								2
`define BASR_ATN										1
`define BASR_ACK										0

//`define START_DMA_SEND_REG						8'd5
`define INPUT_DATA_REG								8'd6
//`define START_DMA_TARGET_RECEIVE_REG		8'd6
//`define RESET_PARITY_INTERRUPT_REG			8'd7
//`define START_DMA_INITIATOR_RECEIVE_REG	8'd7